1. Field of the Invention
The present invention relates generally to a field effect transistor (FET) and a fabrication process thereof. More particularly, the invention relates to a hetero junction FET and a fabrication process thereof.
2. Description of the Related Art
Conventionally, GaAs FETs have been widely employed as elements for high frequency. Particularly, in a high power element, in order to reliably achieve reduction of source resistance and higher gate breakdown voltage(gate tolerance voltage), a multi-stage recessed structure has been employed. FIGS. 1A to 1D are sections showing a recess formation process of a conventional GaAs FET, illustrating the process steps in sequential order. As shown in FIG. 1A, a channel layer 2 consisting of undoped InGaAs or undoped GaAs, is formed on a GaAs layer 1. On the channel layer 2, an Si doped AlGaAs layer 3 is formed. On the AlGaAs layer 3, an Si doped GaAs layer 4 is formed. Also, a wide recess 6 is formed by patterning the GaAs layer 4 employing a mask 5.
Next, as shown in FIG. 1B, a mask 7 is formed covering the upper surface and side surface of the GaAs layer 4 after patterning. Using the mask 7, an upper half of the AlGaAs layer 3 is patterned to form a recess 8 for a gate.
Subsequently, as shown in FIG. 1C, a gate electrode 9 is buried in the recess 8. Furthermore, as shown in FIG. 1D, after removing the mask 7, a source electrode 10 and a drain electrode 11 are selectively formed on the GaAs layer 4.
As set forth above, in a fabrication process of conventional multi-stage recessed structure, the recesses are formed by patterning the masks per each stage and wet etching process with an etching liquid containing sulfuric acid as primary component.
However, in the fabrication process of a FET of the multi-stage recessed structure, exposure steps in number corresponding to number of recesses are required. On the other hand, since wet etching is performed every time of formation of the recess, fluctuation of etching can cause degradation of uniformity and reproduction ability of FET characteristics (particularly threshold voltage).
Particularly, in FIG. 1B, the shape of the recess 8 formed by etching immediately before providing the gate, significantly influences threshold value.
On the other hand, there has been proposed a recess forming technology by selective dry etching of the GaAs layer using the InGaAs layer or AlGaAs layer as an etching stopper (Japanese Unexamined Patent Publication No. Heisei 4-280640). However, a conventional recess forming process by the selective dry etching is primarily directed to realization of the threshold value with high uniformity and no consideration is given for improvement of the FET characteristics per se.
On the other hand, in xe2x80x9cHigh Efficiency Power Module Using HEMT for PDCxe2x80x9d, Preliminary Report of 1996 Institute of Electronics, Communication and Information, Electron-Science Meeting, C-422, there has been disclosed a multistage recessed InGaAS/AlGaAs HEMT, in which an etching stopper layer consisted of nxe2x88x92AlGaAs is provided between an n+GaAs layer and an nxe2x88x92GaAs layer to perform selective etching to form the recessed structure with good controllability and reproduction ability. On the other hand, in FIG. 1 of the above-identified publication, there is disclosed a structure, in which a gate metal and a neighborhood semiconductor layer are not contacted.
In the above-identified known publication, there is no disclosure of a fabrication process of the HEMT. Thus, assuming from the structure, since the mask for forming the gate metal is formed after formation of the two stage recessed structure through at least two lithographic steps, at least three lithographic steps are necessary.
It is an object of the present invention to improve FET characteristics by improving an electrode structure of an FET.
Another object of the present invention is to provide a fabrication process of an FET with lesser fluctuation of characteristics of the FET, such as threshold value or so forth, with lower rising voltage, achieving a hetero junction FET structure having high breakdown voltage (tolerance voltage) characteristics with high uniformity and reproduction ability, and with high yield.
A further object of the present invention is to provide a fabrication process of an FET, in which a gate portion of a hetero junction FET of a multi-stage recessed structure having good characteristics, or an ohmic electrode having a lower contact resistance of the FET can be formed simply with high uniformity and reproduction capacity.
A first aspect of the field effect transistor according to the present invention comprises: a hetero junction semiconductor crystal having at least a channel layer of InGaAs or GaAs, a first AlGaAs layer. a first GaAs layer, a second AlGaAs layer and an n-type second GaAs layer; and an ohmic electrode contacting with said second GaAs layer and said channel layer or with said second GaAs layer and said first AlGaAs layer doped with a donor.
Also, said field effect transistor may-include a gate electrode having a two stage recess structure, in which said first and second GaAs layers are removed in stepwise fashion in the vicinity of said gate electrode forming portion, said gate electrode having a gap between said first GaAs layer and said gate electrode on said first AlGaAs layer, whereby said gate electrode does not contact said first GaAs layer.
A second aspect of the field effect transistor according to the present invention comprises: a hetero junction semiconductor crystal at least including a channel layer of InGaAs or GaAs, a first AlGaAs layer, a first GaAs layer, a second AlGaAs layer and an n-type second GaAs layer, said hetero junction semiconductor crystal having a two stage recess structure removed from said first and second GaAs layers in stepwise fashion in the vicinity of a gate electrode forming portion; and a gate electrode having a gap on said first AlGaAs layer and between said first GaAs layer and said gate electrode, so as to not contact said gate electrode with said first GaAs layer, a gap between a drain region side of said gate electrode and said first GaAs layer being greater than said gap between the source region side of said gate electrode and said first GaAs layer.
A third aspect of the field effect transistor according to the present invention comprises: a hetero junction semiconductor crystal at least including a channel layer of InGaAs or GaAs, a first AlGaAs layer, a first GaAs layer, a second AlGaAs layer and an high concentration n-type second GaAs layer, said hetero junction semiconductor crystal having a two stage recess structure removed from said first and second GaAs layers in stepwise fashion in the vicinity of a gate electrode forming portion; and a gate electrode having a gap on said first AlGaAs layer and between said first GaAs layer and said gate electrode, so as to not contact said gate electrode with said first GaAs layer, a gap between the source region side of said gate electrode and said first GaAs layer being greater than a gap between the drain region side of said gate electrode and said first GaAs layer.
A fourth aspect of the field effect transistor according to the present invention comprises: a hetero junction semiconductor crystal at least including a channel layer of InGaAs or GaAs, an AlGaAs layer, a layer of InAlAs or InAlGaAs and an n-type GaAs layer, said hetero junction semiconductor crystal having a two stage recess structure removed from said n-type GaAs layer and a layer of InAlAs or InAlGsAs in the vicinity of a gate electrode; and a gate electrode provided on said AlGaAs layer, defining a gap between said gate electrode and said layer of InAlAs or InAlGaAs so as to not contact said gate electrode with said layer of InAlAs or InAlGaAs.
The width of said gap between the drain region side of said gate electrode and the layer of InAlAs or InAlGaAs may be different from the width of said gap defined between the source region side of said gate electrode and the layer of InAlAs or InAlGaAs.
A first aspect of the fabrication process of a field effect transistor according to the present invention comprises the steps of: forming a hetero junction semiconductor crystal having a channel layer of InGaAs or GaAs, a first AlGaAs layer, a first GaAs layer, a second AlGaAs layer and an n-type second GaAs layer; forming a two stage recess structure by selective etching of said first GaAs layer and said second GaAs layer with respect to said first AlGaAs layer and said second AlGaAs layer for removing said first and second GaAs layers in stepwise fashion in the vicinity of a gate electrode forming portion; performing etching in a transverse direction with respect to said first GaAs layer by performing excessive etching after extending to said first AlGaAs layer in said selective etching with respect to said first GaAs layer; and forming a gate electrode on said first AlGaAs layer so as to define a gap between said first GaAs layer and said gate electrode, whereby said gate electrode does not contact said first GaAs layer.
A second aspect of the fabrication process of a field effect transistor according to the present invention comprises the steps of: forming a hetero junction semiconductor crystal having a channel layer of InGaAs or GaAs, a first AlGaAs layer, a first GaAs layer, a second AlGaAs layer and an n-type second GaAs layer; selectively etching said first GaAs layer with respect to said first AlGaAs layer after said second GaAs layer and said second AlGaAs layer are removed using a mask which has an opening at an ohmic region; forming an ohmic electrode by deposition and lift off of ohmic metal and heat treatment for alloying so as to contact at least said second GaAs layer and said channel layer or said second GaAs layer and said first AlGaAs layer doped with a donor.
A third aspect of the fabrication process of a field effect transistor employing a hetero junction semiconductor crystal, in which a GaAs layer is stacked on an AlGaAs layer, according to the present invention comprises the steps of: performing anisotropic etching of said GaAs layer in an oblique direction from the upper side of one of regions of a source region and a drain region, by arranging a mask opening a gate electrode portion on the crystal; and forming a gate metal on said AlGaAs layer by deposition and lift off from above in the perpendicular direction with respect to a substrate or an ion beam method.
A fourth aspect of the fabrication process of a field effect transistor employing a hetero junction semiconductor crystal, in which a GaAs layer is stacked on an AlGaAs layer, according to the present invention comprises the steps of: arranging a first mask on said semiconductor crystal and performing an anisotropic etching of said first mask in an oblique direction toward a drain region from the upper side of a source region using a second mask opening a gate electrode portion; etching said GaAs layer using said first mask; and forming a gate electrode by deposition of a gate metal from above in the perpendicular direction with respect to a substrate and lift off or an ion beam method from above in the perpendicular direction with respect to said substrate.
A fifth aspect of the fabrication process of a field effect transistor according to the present invention comprises the steps of: forming a hetero junction semiconductor crystal having a channel layer of InGaAs or GaAs, an AlGaAs layer, a layer of InAlAs or InAlGaAs and an n-type GaAs layer; forming a first stage recess structure removing a part of said n-type GaAs layer; forming a mask for use in pattering a second stage recess structure; selectively etching said layer of InAlAs or InAlGaAs on said AlGaAs layer employing an etchant having a composition of (hydrogen chloride):(water)=1:x(x less than 6); and propagating etching in the transverse direction with respect to the layer of InAlAs or InAlGaAs by excessive etching after selective etching of said layer of InAlAs or InAlGaAs reaches said AlGaAs layer.
With the construction of the FET according to an present invention, a contact portion of the ohmic electrode becomes wide to reduce contact resistance. This invention is applicable not only for a two stage recessed structure but also for a normal FET.
On the other hand, with the structure of the present invention, source resistance can be reduced and a gate breakdown voltage can be improved.
Furthermore, with the structure of the present invention, resistance of the drain electrode can be lowered.
Also, according to the fabrication process of the present invention, the position of the gate electrode can be controlled between the source region and the drain region. Depending upon application of the FET, the position of the gate electrode or the interval between respective electrodes and the gate electrode can be controlled to adjust major characteristic parameters of the FET, such as source resistance, drain resistance, gate breakdown voltage and so forth.
On the other hand, in the present invention, ohmic electrode structure with reduced ohmic resistance can be employed. Also, by employing a structure, in which the position of the gate electrode is controlled between the source region and the drain region, an effect similar to that set forth above can be achieved.
In the present invention, in the step of performing isotropic selective etching of the GaAs layer with respect to the AlGaAs layer, etching propagates in a transverse direction of the GaAs layer by over-etching after etching is reached to the AlGaAs layer. Furthermore, the etching distance in a transverse direction can be easily controlled by an etching period to form the recess having a desired transverse etching length. By this, concentration of the electric field on the drain region side of the gate electrode can be reduced to permit improvement of breakdown voltage characteristics. FIG. 2 is an illustration showing controllability of selective etching obtained by over-etching ratio in the horizontal axis and a side etching amount in the vertical axis. FIG. 2 shows the dependency of the side etching distance relative to the over-etching ratio. For example, side etching of 20 nm can be performed by 100% of over-etching.
On the other hand, by contacting the ohmic electrode with at least one of a high concentration n-type GaAs cap layer and InGaAs channel layer or GaAs channel layer, the contact area of the two-dimensional electron transit layer and the ohmic region can be large to reduce contact resistance. Accordingly, lower rising voltage can be realized.
Furthermore, a compound semiconductor containing In, such as InAlGaAs can be etched by hydrochloric acid. On the other hand, since AlGaAs layer is not dissolved by hydrochloric acid, by employing the hetero junction of the InAlGaAs layer and the AlGaAs layer as the recessed region forming layer, the recessed structure can be formed with good controllability similarly to the step of isotropic selective etching of the GaAs layer and the AlGaAs layer a set forth above.